It is well known that the number of devices that can be supported on a single peripheral component interconnect, or "PCI," bus is limited. In particular, the number of device loads that can be connected to one such bus is, under normal circumstances, approximately ten. Typically, one load is allocated for a motherboard device and two loads each are allocated for expansions slots. In conventional PC systems, three of the ten loads are typically used for three motherboard-based devices, respectively, one load is allocated to a riser connector, when a riser card implementation is used to support expansion slots is used, leaving six loads for three expansion slots into which expansion cards can be plugged. Accordingly, to enable more than two or three PCI expansion slots to be supported on a single PC, it has been known include in a PC an additional PCI bus (the "secondary PCI bus"), which is connected to the first PCI bus (the "primary PCI bus") via a device commonly designated as a PCI-to-PCI bridge.
A PCI-to-PCI bridge is typically implemented as an integrated circuit ("IC") chip connected to a primary PCI bus in front of the bridge and forming a secondary PCI bus behind the bridge. The bridge only takes up one device load on the primary bus and provides for an additional ten device loads behind the bridge via the secondary bus. These additional loads are almost totally electrically isolated from the primary bus.
FIG. 1 illustrates a PC 10 comprising a typical PCI configuration wherein a PCI-to-PCI bridge 12 is used to increase the number of PCI devices that can be supported. In particular, the PC 10 includes a host 14, which will include a host CPU, system memory, and ROM BIOS, residing on a host bus 16. The host bus 16 is connected to a primary PCI bus 18 via a host-to-PCI bridge 20. The primary PCI bus 18 is further connected to a secondary PCI bus 22, on which a display 23 resides, via the PCI-to-PCI bridge 12. In the illustrated embodiment, a single PCI device 26 resides on the primary PCI bus 18. In addition, two primary expansion slots 28a, 28b, for enabling additional PCI devices to be connected to the primary PCI bus 18, are provided thereon. Similarly, two PCI devices 32, 34, reside directly on the secondary PCI bus 22 and three secondary expansion slots 36a-36c are provided on the secondary PCI bus 22.
It should be understood that more than the number of expansion slots shown in FIG. 1 may be connected to the buses 18 and 22. Moreover, although not shown, will be recognized that the slots 28a-28b, 36a-36c, may be connected to the respective bus 18, 22, via an appropriate riser card.
In operation, each PCI 2.x-compliant device, such as the devices 26, 32 and 34, residing on a PCI bus requests a certain address range through which other devices can access the PCI device. Each device requests some number of consecutive addresses and the host 14 assigns chunks of the I/O space to the device. For example, if the device 26 requests a 256 byte address space, the host 14 may assign the device the contiguous address space beginning at address FEECh. The device 26 will then use the assigned address as a base, or lower, address limit and the assigned address plus 256 bytes as the upper address limit. Thereafter, any writes to or reads from this I/O space will be claimed by the device 26 and the device 26 will respond appropriately. A PCI-to-PCI bridge, such as the bridge 12, being a PCI device, operates in the same fashion. Specifically, it requests a contiguous address space, in particular, 4K, for its address space. The bridge 12 then divides this space and issues segments of it to the devices residing on the secondary PCI bus 22, such as devices 32, 34, and slots 36a-36c. In this manner, each device and slot that resides on the secondary bus 22 will be assigned its own address space comprising part of the address space assigned to the bridge 12.
When a device on the primary PCI bus 18, such as the device 26, wants to communicate with a device on the secondary PCI bus 22, such as the device 32, the device 26 will attempt to write to or read from the address space assigned to the bridge 12 and allocated by the bridge 12 to the device 32. The bridge 12 will accept the transaction and forward it to the device 32.
There are certain problems inherent in the use of a conventional PCI-to-PCI bridge in the manner described above. First, there are many PCI devices, in particular video cards and IDE cards, that are not completely PCI compliant. Such devices are hereinafter referred to as "semi-compliant PCI devices." Semi-compliant PCI devices have inherited an addressing scheme from the industry standard architecture ("ISA") standard that allows an expansion card to specify a noncontiguous address space. In addition, semi-compliant PCI devices have designated addresses that do not apply to the PCI remapping feature as defined by PCI 2.x specifications. Because PCI-to-PCI bridges that are currently commercially available only allocate to themselves a single contiguous I/O address range and cannot selectively accept certain single noncontiguous addresses, semi-compliant devices will not operate properly behind current PCI-to-PCI bridges. Moreover, although current PCI-to-PCI bridges do possess a special feature that enables them selectively to forward certain noncontiguous addresses in the VGA space according to the VGA specification, they lack two or more addresses that are not in the specification, but that most video devices require. As a result, the behavior observed by a user as a result of plugging a video card into one of the secondary expansion slots 36a-36c, which are generally externally indistinguishable from the primary expansion slots 28a, 28b, would be a lack of a video image; i.e., a blank screen. Clearly, this is an unacceptable result.
Additionally, some PCI devices, although capable of functioning behind a PCI-to-PCI bridge, incur a performance penalty in doing so. This is primarily due to the fact that any data must go through an intermediate device (i.e., the bridge 12) on the way to and from the device, thereby resulting in a latency. For ease of discussion, such devices will also be referred to herein as "semi-compliant PCI devices." Unless notified, a user might remain unaware that the device would operate more efficiently if inserted in one of the primary PCI slots.
Therefore, what is needed is a technique for detecting the insertion of a semi-compliant PCI device into a secondary expansion slot and instructing regarding same.